A modern digital chip begins as a written idea and ends as a set of geometric shapes that a fab can print onto silicon. Between those two points sits a long chain of design steps, usually summarized as the “RTL to GDSII” flow. Knowing the stages helps you see why chip projects take so long and where specialized engineers fit.

The Big Picture

Think of chip design as progressively adding physical detail. At the start, the design is a description of behavior. By the end, it is a precise drawing of every transistor and wire. Each stage takes the previous result, transforms it, and checks that nothing important was lost along the way.

Stage 1: Specification and Architecture

Before any code is written, the team decides what the chip must do. Which functions does it need? What performance, power and cost targets apply? What interfaces must it support? Architects divide the chip into blocks, choose which parts to design in-house and which to license as reusable IP, and estimate area and power.

Mistakes at this stage are the most expensive, because everything downstream builds on them.

Stage 2: RTL Design

RTL stands for register-transfer level. Engineers describe the chip’s behavior using a hardware description language such as Verilog, SystemVerilog or VHDL. The code specifies how data moves between registers and what logic operates on it on each clock cycle.

Despite looking like software, RTL describes parallel hardware. A line of RTL does not run in sequence; it becomes circuitry that exists simultaneously with everything else.

Stage 3: Functional Verification

Verification checks that the RTL does what the specification says. Teams write testbenches, run simulations, apply random and directed tests, and often use formal methods to prove certain properties. Verification typically occupies a very large share of project effort, because bugs found after manufacturing are costly to fix.

Stage 4: Logic Synthesis

Synthesis tools translate RTL into a netlist of logic gates drawn from a standard cell library supplied for the target manufacturing process. The tools optimize for timing, area and power based on constraints the team provides. The result is a gate-level description that no longer says what the design means, only which cells connect to which.

Stage 5: Design for Test

Manufactured chips must be testable. Engineers add structures such as scan chains that let test equipment control and observe internal states, plus built-in self-test logic for memories. This adds a little area but makes it possible to screen out defective parts later.

Stage 6: Floorplanning, Placement and Routing

Now the design becomes geometry. Floorplanning decides where major blocks sit and where power and input/output connections go. Placement positions each standard cell. Clock tree synthesis distributes the clock signal so that registers receive it at nearly the same time. Routing draws the metal wires that connect everything across multiple layers.

This stage is often called physical design, and it is a continuous trade between timing, congestion, power and area.

Stage 7: Signoff

Signoff is the final set of checks before release. Static timing analysis confirms the design meets timing under a range of manufacturing and operating conditions. Power analysis checks consumption and power delivery. Physical verification includes design rule checks, which confirm the layout follows the manufacturer’s rules, and layout-versus-schematic checks, which confirm the drawn layout matches the intended netlist.

Stage 8: Tape-Out and GDSII

When signoff passes, the team releases the final layout in a file format such as GDSII (or its successor OASIS) to the manufacturer. This release is called tape-out, a term inherited from the era when data was shipped on magnetic tape. From here, masks are made and wafers are fabricated.

Flow Summary Table

Stage	Input	Output	Main concern
Specification	Product needs	Architecture	Getting requirements right
RTL design	Architecture	HDL code	Correct, synthesizable behavior
Verification	RTL, tests	Confidence in function	Catching bugs early
Synthesis	RTL, constraints	Gate netlist	Timing, area, power
Design for test	Netlist	Testable netlist	Manufacturing test coverage
Physical design	Netlist	Layout	Timing closure, routability
Signoff	Layout	Pass/fail reports	Meeting all checks
Tape-out	Final layout	GDSII/OASIS file	Release readiness

A Hypothetical Example

Imagine a team designing a small controller chip. During synthesis, a path between two registers fails the timing target. The team has options: rewrite part of the RTL to simplify the logic, adjust synthesis constraints, change the floorplan so the blocks sit closer together, or relax the target clock speed. Each choice trades effort, area or performance. Seasoned engineers learn which lever to pull first, and that judgment is much of what the job is.

Iteration Is Normal

The flow is not a straight line. Findings in physical design often send engineers back to RTL or constraints. Verification continues alongside implementation. Real projects loop through these stages many times before signoff passes.

Analog and Mixed-Signal Differences

Analog circuits, such as amplifiers and sensors, follow a more manual flow with transistor-level schematics, simulation and hand-drawn layout. Many chips combine digital and analog parts, so teams run both flows and integrate them carefully.

Frequently Asked Questions

What does RTL stand for? Register-transfer level, a way of describing hardware by how data moves between registers and the logic between them.

What is GDSII? A long-standing file format that stores the geometric layout of a chip, layer by layer, for use in mask making. OASIS is a newer, more compact alternative.

Why is verification so time-consuming? Chips are complex, bugs may appear only in rare situations, and fixing a flaw after fabrication can be very expensive. Teams therefore invest heavily in finding problems early.

What is timing closure? The process of adjusting the design until all signal paths meet their timing requirements across the required operating conditions.

Do all chips follow this exact flow? The broad structure is common to digital designs, but details differ by company, tools, process and chip type. Check your tool and foundry documentation for specifics.

Next Step

Sketch the flow above on one page and write a single sentence under each stage describing the question it answers. Then pick one stage, such as verification or physical design, and read introductory material on it to decide where you would like to go deeper.