Sooner or later a hardware team hits the question: do we buy a standard part, program an FPGA, or build our own chip? People often frame it as a technical contest. It is mostly a question about money, schedule and how sure you are of your requirements.

The three options in plain terms

Off-the-shelf silicon means a chip someone else designed and sells to many customers, such as a microcontroller, a processor or an application-specific standard product. You write software and design a board around it. The cost of the chip’s design is spread across every customer.

An FPGA is a chip whose logic can be configured after manufacturing. You describe hardware in a hardware description language, and the device implements it. You get custom digital behavior without paying for your own manufacturing run, and you can change it later.

An ASIC is a chip designed for your application and manufactured for you. It can be efficient in power, performance and per-unit cost at volume, but it requires a large upfront investment and a design that must be right, because changing it means another manufacturing cycle.

Where the money goes

The key distinction is the cost structure.

An ASIC carries high non-recurring engineering (NRE) cost: design work, verification, tool licenses, mask sets and prototype runs. Once that is paid, the cost per unit can be low. An FPGA carries little NRE but a higher cost per unit, since you pay for the flexibility built into the device. A standard part has essentially no NRE for you, with a per-unit price set by the supplier.

That produces the classic crossover. At low volume, the lower-NRE option wins. At sufficiently high volume, the ASIC’s lower unit cost can repay its upfront cost. Where exactly the crossover sits depends on your design, the process, and current quotes, so get real numbers from vendors and foundry partners instead of trusting rules of thumb you find online.

Comparison

Factor	Standard chip	FPGA	ASIC
Upfront cost	Lowest	Low to moderate	High
Unit cost at high volume	Set by supplier	Usually highest	Potentially lowest
Time to first working product	Fastest	Fast	Slowest
Ability to fix a mistake	Software or board change	Reprogram	Often a new manufacturing cycle
Power and size optimization	Limited to what exists	Moderate	Highest potential
Differentiation	Low unless in software	Medium to high	Highest
Supply dependence	On the vendor’s product line	On the FPGA vendor	On foundry and packaging partners

Questions that actually decide it

How stable are your requirements? If the algorithm or protocol is still changing, an ASIC is dangerous. An FPGA lets you update after deployment. A team that has changed its spec three times this year should not commit to masks.

What volume do you realistically expect? Be honest, and use a range. Optimistic volume projections are the most common reason custom chips disappoint financially.

Is power or size the binding constraint? If a standard part cannot hit the battery life or physical size you need, custom silicon starts to look more attractive. If it can, the argument weakens.

Do you have the team and tools? Verification, physical design and test planning are real disciplines. Without experienced people, or partners who have them, a first ASIC is a hazardous project.

What does your product lifetime look like? Long-lived products may care about the supplier’s longevity commitments as much as technical fit.

A hypothetical path

Imagine a company building a specialized signal-processing box in small quantities for industrial customers. They begin with a standard processor and software. It cannot keep up with one processing stage, so they move that stage to an FPGA and keep the rest on the processor. Customers like it, requirements settle after a couple of releases, and volume grows.

At that point they have good evidence for an ASIC conversation: a proven design running on an FPGA, stable requirements, and real volume forecasts. Moving the FPGA design into an ASIC flow is a common route, because the FPGA stage acted as a low-risk prototype. If volume had stayed small, they would probably have stayed on the FPGA, and that would have been the correct decision.

Mistakes that cost the most

• Choosing an ASIC to look serious. Custom silicon is a means, not a badge.
• Underestimating verification. A respin is expensive and slow. Plan verification time seriously.
• Ignoring the software. Chips without a usable software stack and drivers do not become products.
• Forgetting test and packaging. These have costs and lead times of their own.
• Treating the FPGA as free of risk. Supply, long-term availability and tool flows still matter. Check the vendor’s current documentation and product lifecycle policy.
• Skipping a middle path. Sometimes a standard part with a small companion device is enough.

Frequently Asked Questions

At what volume does an ASIC make sense? There is no universal number. It depends on NRE, process choice and per-unit savings. Request quotes and model a range of volumes rather than relying on a general figure.

Can I prototype an ASIC design on an FPGA? Yes, this is common practice, and it helps validate functionality and software early. Some differences in timing and power remain, so it does not replace full ASIC verification.

Is an FPGA always slower than an ASIC? Generally an ASIC can achieve better performance and power for a fixed function, but a well-chosen FPGA is sufficient for many products. Compare against your actual requirements.

What is a structured or semi-custom option? Some approaches reduce NRE by customizing only part of the manufacturing layers or by using pre-built blocks. Availability and terms change, so ask current suppliers.

Do standard parts limit differentiation? Hardware differentiation is limited, but software, system design, and integration can still set a product apart.

Next Step

Write a one-page decision brief. List your requirement stability, a low, expected and high volume forecast, power and size limits, and your team’s experience. Then request budgetary quotes for the standard-part and FPGA routes, and an exploratory estimate for the ASIC route. Comparing three real numbers will end most circular debates.